1. Field of the Invention
The present invention relates to a structure in which electric field through a thin film field effect transistor using a polycrystalline silicon layer of a thin film as a channel layer can be decreased and to a manufacturing method of the thin film field effect transistor.
2. Description of the Background Art
A so-called thin film transistor (TFT) is one of types of insulated field effect transistors structured to have semiconductor thin films formed on insulating substrates and channel regions within the thin films.
FIG. 7 is a sectional structural view of a conventional thin film transistor. In the conventional thin film transistor, a gate electrode 5 of a polycrystalline silicon layer is formed on a surface of an insulating substrate or insulating layer 1. A gate insulating layer 7 of an oxide film or the like is formed on the surfaces of insulating substrate 1 and gate electrode 5. A semiconductor layer 8 of polycrystalline silicon or single crystalline silicon is formed on a surface of gate insulating layer 7. A pair of source/drain regions 14, 14 are formed in the semiconductor layer 8, and a channel region 12 is formed between these source/drain regions 14, 14. The surface of semiconductor layer 8 is covered with an interlayer insulating layer 15. Interconnection layers 16 are connected to source/drain regions 14, 14, respectively, through contact holes formed in interlayer insulating layer 15. Such a type of a gate electrode 5 being formed under channel region 12 is called a bottom gate type thin film transistor. FIG. 16 (a) is an equivalent circuit diagram of the bottom gate thin film transistor.
Manufacturing steps of the thin film transistor shown in FIG. 7 will be described. FIGS. 8 through 13 are sectional structural views sequentially showing respective manufacturing steps of the thin film transistor (a first step through a sixth step).
First, as shown in FIG. 8, a polycrystal silicon layer 2 is formed on the surface of insulating layer substrate 1 using a CVD (Chemical Vapor Deposition) method. A resist pattern 4 is formed on the surface of polycrystalline silicon layer 2 using a photolithography method and an etching method. Then, using a resist pattern 4 as a mask, polycrystalline silicon layer 2 is etched and a gate electrode 5 is formed.
Next, as shown in FIG. 9, a gate insulating film 7 and a semiconductor layer 8 of polycrystalline silicon or single crystalline silicon are formed on the whole wafer. A resist pattern 24 to define shapes of active regions is then formed on the surface of semiconductor layer 8 using a photolithography method. Using the resist pattern 24 as a mask, semiconductor layer 8 is patterned. After the resist pattern 24 is removed, impurities of a first type conductivity are ion-implanted into semiconductor layer 8 in a dose of 0-5.times.10.sup.13 /cm.sup.2.
As shown in FIG. 10, a resist pattern 25 is formed on the surface of a region which is to be a channel region of semiconductor layer 8 using a photolithography method. Using resist pattern 25 as a mask, impurity ions 33 of a second type conductivity are ion-implanted into semiconductor layer 8 in a dose of 5.times.10.sup.14 -1.times.10.sup.16 /cm.sup.2, so that a pair of source/drain regions 14, 14 are formed in semiconductor layer 8.
As shown in FIG. 11, an interlayer insulating film 15 is formed on the whole surface. On the surface of interlayer insulating layer 15, resist pattern 26 is formed for forming contact holes. Using resist pattern 26 as a mask, interlayer insulating layer 15 is etched to form contact holes reaching source/drain regions 14, 14.
As shown in FIG. 12, after resist pattern 26 is removed, interconnection layers 16 are formed within contact holes and on the surface of interlayer insulating layer 15 and is patterned to a prescribed interconnection pattern. By following the above steps, wafer process of a thin film transistor shown in FIG. 12 (corresponding to FIG. 7) is finished.
A bottom gate type thin film transistor manufactured by the above stated method has source/drain regions formed by ion implantation using resist 25 as a mask, as shown in FIG. 10. A problem sometimes arises that gate electrode 5 and resist pattern 25 for forming source/drain regions are not in register because of alignment errors of a mask for forming a resist pattern. FIG. 13 is a sectional structural view showing positions of resist pattern 25 and source/drain regions 14, 14 when an alignment error occurs. When such an alignment error shown in the figure occurs, one of source/drain regions 14 is separated from gate electrode 5 and a so-called offset structure is formed. When such a thin film transistor of an offset structure is formed, a problem arises that transistor characteristics deteriorate. In particular, as a device is miniaturized and a channel length becomes 1 .mu.m or shorter than 1 .mu.m, the problem of an alignment error of a mask has been more significant than ever.
In order to avoid the alignment error of a mask, a thin film transistor formed by a method in which an alignment of gate electrode with source/drain regions is carried out using a self-alignment technology has been conceived. FIG. 14 is a sectional structural view of a bottom gate type thin film transistor having source/drain regions formed by the self-alignment technology. The thin film transistor shown is described, for example, in Symposium on VLSI Technology p.8, Sep. 10-12, 1984. FIG. 16 (b) is an equivalent circuit diagram of the thin film transistor shown in FIG. 14. As shown in FIGS. 14 and 16 (b), the thin film transistor includes a pair of source/drain regions 14, 14 formed in semiconductor layer 8 located on the surface of insulating substrate 1 and a source/drain region 14 formed in semiconductor layer 8 located above gate electrode 5. Channel regions 12, 12 are formed in semiconductor layer 8 located on the sidewalls of gate electrode 2. Hence, this thin film transistor has two transistors formed on the sidewalls of the gate and connected in series.
A method of manufacturing a thin film transistor shown in FIG. 14 will be described. Manufacturing step of a first conventional example shown in FIGS. 8 and 9 can be also used in manufacturing steps of the film transistor shown in FIG. 14. Therefore, the description of the steps shown in FIGS. 8 and 9 will not be repeated. Following the steps shown in FIG. 9, as shown in FIG. 15, impurity ions 34 are ion-implanted vertically into semiconductor layer 8. By this ion implantation, semiconductor layer 8 has impurities implanted only in a region extending on the surface of insulating substrate 1 and a region above gate electrode 2 to form source/drain regions 14, 14, but not in a region on the sidewalls of gate electrode 2 which are to be channel regions 12, 12.
Thereafter interlayer insulating layer 15 and interconnection layer 16 are formed as in the first conventional example.
However, in the conventional bottom gate type thin film transistor shown in FIG. 14, a problem exists that large electric field strength is generated in a region of semiconductor layer 8 where a source/drain region 14 is superimposed on gate electrode 2 resulting in an increase in leakage current. Since channel regions 12, 12 are formed on the sidewalls of gate electrode 2, a channel length is short and therefore a problem of a decrease in a breakdown voltage between source/drain regions 14, 14 arises.